Computer systems and processor architectures, in particular, can use various types communication networks and protocols to exchange information between agents, such as electronic devices, within those systems and architectures. Multiple processing elements (“processing cores”) in a microprocessor, for example, use caching agents to store, retrieve, and exchange data between the various cores of the microprocessor. Likewise, computer systems in which single or multiple core microprocessors are interconnected may use caching agents to store, retrieve and exchange data between the microprocessors or other agents.
In electronic networks, cached data is managed and exchanged according to certain rules, or “protocol,” such that coherency is maintained among the various caches and the devices, such as processing cores, that use the cached data. Caching activity across these devices directly serviced by the caches, such as lookup operations, store operations, invalidation operations, and data transfer operations, can be managed by logic or software routine (collectively or individually referred to as a “cache agent”), such that cache coherency is maintained among the various caches and cache agents. Caching activity within or outside of a microprocessor, such as snoop resolution, write-backs, fills, requests, and conflict resolution, can be managed by logic or software routine (collectively or individually referred to as a “protocol agent”), such that coherency is maintained among the various cache agents and processing cores within the microprocessor and among agents external to the microprocessor. In some prior art multi-core or single-core processors, for example, the caching agent is coupled to a specific coherence protocol agent, which may be physically integrated within the caching agent to which it corresponds. This means that the same circuit and/or software routine may be responsible for implementing cache operations, such as requests, dirty block replacement, fills, reads, etc., as the protocol for managing these operations.
FIG. 1 illustrates a prior art microprocessor having a number of caching agents, each having circuitry to implement the caching protocol used among the caching agents of the microprocessor. In the prior art processor of FIG. 1, each caching agent is responsible for implementing and keeping track of the cache protocol as applied to itself. That is, each cache agent is coupled to a protocol agent, such that the same unit is responsible for both cache operations and the coherence protocol. Unfortunately, this “decentralized” caching protocol architecture requires redundant use of protocol logic and/or software to maintain the caching protocol among all caching agents within the processor or computer system to which the protocol corresponds. In the case of the protocol being implemented using complementary metal-oxide-semiconductor (CMOS) logic devices, this can result in substantial power consumption by the processor or system, especially in multi-core processors having a number of caching agents.
Furthermore, the prior art caching architecture of FIG. 1 may be somewhat bandwidth limited in the amount of caching traffic supported among the caching agents, as each caching agent has to share the same bus, cache agent ports, and cache agent queuing structure that facilitate communication among the various caching agents.
To correctly identify transactions in a system, often transaction IDs are used. These transaction IDs are often assigned based on a number of factors. However, if there is one or more dependencies upon which selection of a transaction ID is based, then there can be latency added into the processing of the transaction itself. This is especially true in the case where the processing of a transaction occurs in a pipeline with various stages of the pipeline dependent on previous stages. Such added latencies can affect performance and should be avoided.